1. Field of the Invention
The present disclosure generally relates to the formation of integrated circuits, and, more particularly, to the formation of semiconductor structures comprising field effect transistors having stressed channel regions.
2. Description of the Related Art
Integrated circuits comprise a large number of individual circuit elements, e.g., transistors, capacitors and resistors. These elements are connected internally to form complex circuits, such as memory devices, logic devices and microprocessors. The performance of integrated circuits can be improved by increasing the number of functional elements per circuit in order to increase their functionality and/or by increasing the speed of operation of the circuit elements. A reduction of feature sizes allows the formation of a greater number of circuit elements on the same area, hence allowing an extension of the functionality of the circuit, and also reduces signal propagation delays, thus making an increase of the speed of operation of circuit elements possible.
Field effect transistors are used as switching elements in integrated circuits. They provide a means to control a current flowing through a channel region located between a source region and a drain region. The source region and the drain region are highly doped. In N-type transistors, the source and drain regions are doped with an N-type dopant. Conversely, in P-type transistors, the source and drain regions are doped with a P-type dopant. The doping of the channel region is inverse to the doping of the source region and the drain region. The conductivity of the channel region is controlled by a gate voltage applied to a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. Depending on the gate voltage, the channel region may be switched between a conductive “on” state and a substantially non-conductive “off” state.
When reducing the size of field effect transistors, it is important to maintain a high conductivity of the channel region in the “on” state. The conductivity of the channel region in the “on” state depends on the dopant concentration in the channel region, the mobility of the charge carriers, the extension of the channel region in the width direction of the transistor and on the distance between the source region and the drain region, which is commonly denoted as “channel length.” While a reduction of the width of the channel region leads to a decrease of the channel conductivity, a reduction of the channel length enhances the channel conductivity. An increase of the charge carrier mobility leads to an increase of the channel conductivity.
As feature sizes are reduced, the extension of the channel region in the width direction is also reduced. A reduction of the channel length entails a plurality of issues associated therewith. First, advanced techniques of photolithography and etching have to be provided in order to reliably and reproducibly create transistors having short channel lengths. Moreover, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the source region and in the drain region in order to provide a low sheet resistivity and a low contact resistivity in combination with a desired channel controllability.
In view of the problems associated with a further reduction of the channel length, it has been proposed to also enhance the performance of field effect transistors by increasing the charge carrier mobility in the channel region. In principle, at least two approaches may be used to increase the charge carrier mobility.
First, the dopant concentration in the channel region may be reduced. Thus, the probability of scattering events of charge carriers in the channel region is reduced, which leads to an increase of the conductivity of the channel region. Reducing the dopant concentration in the channel region, however, significantly affects the threshold voltage of the transistor device. This makes the reduction of dopant concentration a less attractive approach.
Second, the lattice structure in the channel region may be modified by creating tensile or compressive stress. This leads to a modified mobility of electrons and holes, respectively. Depending on the magnitude of the stress, a compressive stress may significantly increase the mobility of holes in a silicon layer. The mobility of electrons may be increased by providing a silicon layer having a tensile stress.
A method of forming a field effect transistor wherein the channel region is formed in stressed silicon will be described in the following with reference to FIGS. 1a-1b. FIG. 1a shows a schematic cross-sectional view of a semiconductor structure 100 in a first stage of a manufacturing process according to the state of the art.
The semiconductor structure 100 comprises a substrate 101. The substrate 101 comprises a first transistor element 102 and a second transistor element 103. The first transistor element 102 comprises an active region 105 formed in the substrate 101. A gate electrode 110 is formed over a channel region 123 in the substrate 101 and separated therefrom by a gate insulation layer 121. The gate electrode 110 is flanked by inner sidewall spacers 109, 111 and outer sidewall spacers 108, 112. In the substrate 101, a source region 107 and a drain region 113 are formed adjacent the gate electrode 101.
Similarly, the second transistor element 103 comprises an active region 106, a gate electrode 117, a gate insulation layer 122, inner sidewall spacers 116, 118, outer sidewall spacers 115, 119, a source region 114, a drain region 120 and a channel region 124. A trench isolation structure 104 provides electrical insulation between the first transistor element 102 and the second transistor element 103. Additionally, the trench isolation structure 104 may provide electrical insulation between the transistor elements 102, 103 and other electrical elements in the semiconductor structure 100.
The first transistor element 102 and the second transistor element 103, as well as the trench isolation structure 104, may be formed by means of well-known methods of photo-lithography, etching, deposition, ion implantation and oxidation. In particular, the active regions 105, 106, the source regions 107, 114 and the drain regions 113, 120 may be formed by implanting ions of dopant materials into the semiconductor structure 100.
In some examples of methods of forming a semiconductor structure according to the state of the art, the first transistor element 102 can be an N-type transistor and the second transistor element 103 can be a P-type transistor. In such methods, the active region 105 may comprise a P-type dopant and the active region 106 may comprise an N-type dopant. The source region 107 and the drain region 113 comprise an N-type dopant. The source region 114 and the drain region 120 comprise a P-type dopant. In ion implantation processes, one of the field effect transistor elements 102, 103 may be covered with a mask which may, for example, comprise a photoresist, while the other of the field effect transistor elements 102, 103 is irradiated with ions. Thus, an undesirable introduction of dopants which are not in line with the type of the transistor elements 102, 103 may be avoided.
In the formation of the source regions 107, 114 and the drain regions 113, 120, a plurality of implantation processes may be performed for each of the transistor elements 102, 103. First, ion implantation processes may be formed before the formation of the inner sidewall spacers 109, 111, 116, 118 and the outer sidewall spacers 108, 112, 115, 119. Thereafter, the inner sidewall spacers 109, 111, 116, 118 can be formed by means of known methods comprising an isotropic deposition of a material layer and an anisotropic etching process.
After the formation of the inner sidewall spacers 109, 111, 116, 118, second ion implantation processes can be performed. In the second ion implantation processes, the inner sidewall spacers 109, 111, 116, 118 absorb ions impinging in the vicinity of the gate electrodes 110, 117. Hence, in the second ion implantation process, substantially no dopants are introduced in the vicinity of the gate electrodes 110, 117. Thus, dopants may be selectively introduced into portions of the source regions 107, 114 and the drain regions 113, 120 having a distance from the gate electrodes 110, 117 which is greater than a thickness of the inner sidewall spacers 109, 111, 116, 118.
Thereafter, the outer sidewall spacers 108, 112, 115, 119 are formed and third ion implantation processes are performed. In the third ion implantation processes, both the inner sidewall spacers 109, 111, 116, 118 and the outer sidewall spacers 108, 112, 115, 119 absorb ions impinging on the semiconductor structure 100. Thus, dopants may be selectively introduced into portions of the source regions 107, 114 and the drain regions 113, 120 having a distance from the gate electrodes 110, 117 which is greater than a sum of the thickness of the inner sidewall spacers 109, 111, 116, 118 and a thickness of the outer sidewall spacers 108, 112, 115, 119.
Hence, dopant profiles in the source regions 107, 113 and the drain regions 114, 120 may be controlled by varying a thickness of the inner sidewall spacers 109, 111, 116, 118, a thickness of the outer sidewall spacers 108, 112, 115, 119 and ion doses applied in the first, second and third ion implantation processes. Thus, highly sophisticated dopant profiles may be created in the first transistor element 102 and the second transistor element 103.
In the ion implantation processes performed in the formation of the source regions 107, 114 and the drain regions 113, 120, atoms of the substrate 101 may be pushed away from their sites in the crystal lattice of the material of the substrate 101. In modern methods of manufacturing a semiconductor structure, ion doses applied in the formation of the source regions 107, 114 and the drain regions 113, 120 may be sufficient to destroy the crystalline order of the material of the substrate 101, such that an amorphous material is obtained in the source regions 107, 114 and the drain regions 113, 120.
FIG. 1b shows a schematic cross-sectional view of the semiconductor structure 100 in a later stage of the manufacturing process according to the state of the art. A liner layer 125 and a stress-creating layer 126 are formed over the first transistor element 102 and the second transistor element 103. The stress-creating layer 126 may comprise a relatively hard material such as silicon nitride and the liner layer 125 may comprise silicon dioxide. In the formation of the liner layer 125 and the stress-creating layer 126, methods of deposition well known to persons skilled in the art, such as chemical vapor deposition and/or plasma enhanced chemical vapor deposition, may be employed.
A portion of the stress-creating layer 126 covering the second transistor element 103 may be removed. To this end, a mask comprising a photoresist covering the first transistor element 102 may be formed. Thereafter, an etching process adapted to selectively remove the material of the stress-creating layer 126 can be performed. An etchant used in the etching process may be adapted such that the liner layer 125 is substantially not affected by the etching process. Thus, the etching process may be stopped as soon as the stress-creating layer 126 is removed. Portions of the stress-creating layer 126 over the first transistor element 102 are protected from being etched by the mask and remain on the surface of the semiconductor structure 100. After the etching process, the mask can be removed by means of a known resist strip process.
An annealing process is performed. In the annealing process, the semiconductor structure 100 is exposed to an elevated temperature for a predetermined time. In the annealing process, amorphous material in the source regions 107, 114 and the drain regions 113, 120 re-crystallizes. In the re-crystallization process, atoms in the source regions 107, 114 and the drain regions 113, 120 adapt to the crystalline order of portions of the substrate 101 below the source regions 107, 114 and the drain regions 113, 120. Thus, a crystalline material may be obtained in the source regions 107, 114 and the drain regions 113, 120.
Amorphous semiconductor materials may have a lower density than crystalline semiconductor material. In particular, a density of amorphous silicon is lower than a density of crystalline silicon. Therefore, the material of the source regions 107, 114 and the drain regions 113, 120 tends to reduce its volume in the re-crystallization process.
In the first transistor element 102, the stress-creating layer 126, which, as detailed above, may comprise a relatively hard material such as silicon nitride, may prevent a reduction of the volume of the material in the source region 107 and the drain region 113, since the material of the source region 107 and the drain region 113 adheres to the stress-creating layer 126, and the hardness of the stress-creating layer 126 may prevent a deformation of the stress-creating layer 126.
Therefore, the atoms in the source region 107 and the drain region 113 may arrange at a distance which is greater than the bulk lattice constant of the material of the substrate 101. Thus, an intrinsic tensile stress can be created in the source region 107, the drain region 113 and in a channel region 121 of the first transistor element 102.
In the second transistor element 103, the volume of the material of the source region 114 and the drain region 120 may change during the annealing process. Hence, the source region 114, the drain regions 120, as well as a channel region 122 of the second transistor element 103, may be substantially unstressed.
The annealing process may also be employed in order to activate the dopant materials in the source regions 107, 114 and the drain regions 113, 120 such that they may act as electron donors or acceptors.
After the annealing process, the stress-creating layer 126 and the liner layer 125 may be removed by means of an etching process. The intrinsic stress in the source region 107, the drain region 113 and the channel region 123 of the first transistor element 102, however, may be maintained after the removal of the stress-creating layer 126. This phenomenon is known to persons skilled in the art as “stress memorization.”
A problem of the above method of forming a semiconductor structure is that, in the annealing process, dopant materials in the source regions 107, 114 and the drain regions 113, 120 may diffuse. Hence, sophisticated dopant profiles created by means of the first to third ion implantation process may be blurred.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.